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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM
Features

Functional Description
The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25[1] SRAM integrates 2M x 36/4M x 18/1M x 72 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) is active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self timed Write cycle. This part supports Byte Write operations (see "Pin Definitions" on page 7 and "Truth Table" on page 10 for further details). Write cycles can be one to two or four bytes wide, as controlled by the byte write control inputs. When it is active LOW, GW writes all bytes.
Supports bus operation up to 250 MHz Available speed grades are 250, 200, and 167 MHz Registered inputs and outputs for pipelined operation 2.5V core power supply 2.5V IO operation Fast clock-to-output time 3.0 ns (for 250 MHz device) Provide high performance 3-1-1-1 access rate User selectable burst counter supporting Intel(R) Pentium(R) interleaved or linear burst sequences Separate processor and controller address strobes Synchronous self timed writes Asynchronous output enable Single cycle chip deselect CY7C1480BV25, CY7C1482BV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1486BV25 available in Pb-free and non-Pb-free 209-ball FBGA package IEEE 1149.1 JTAG-Compatible Boundary Scan "ZZ" Sleep Mode option

Selection Guide
Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 250 MHz 3.0 450 120 200 MHz 3.0 450 120 167 MHz 3.4 400 120 Unit ns mA mA
Note 1. For best practices recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation Document #: 001-15143 Rev. *D
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 29, 2008
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Logic Block Diagram - CY7C1480BV25 (2M x 36)
A 0, A1, A
ADDRESS REGISTER
2
A [1:0]
MODE ADV CLK
Q1
ADSC ADSP
BW D DQ D ,DQP D BYTE WRITE REGISTER DQ C ,DQP C BYTE WRITE REGISTER DQ B ,DQP B BYTE WRITE REGISTER DQ A ,DQP A BYTE WRITE REGISTER
BURST COUNTER CLR AND LOGIC
Q0
DQ D ,DQPD BYTE WRITE DRIVER DQ C ,DQP C BYTE WRITE DRIVER DQ B ,DQP B BYTE WRITE DRIVER DQ A ,DQP A BYTE WRITE DRIVER
BW C
MEMORY ARRAY
SENSE AMPS
OUTPUT REGISTERS
OUTPUT BUFFERS E
BW B
DQs DQP A DQP B DQP C DQP D
BW A BWE
GW CE1 CE2 CE3 OE
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
Logic Block Diagram - CY7C1482BV25 (4M x 18)
A0, A1, A
MODE
ADDRESS REGISTER
2 A[1:0]
ADV CLK
BURST Q1 COUNTER AND LOGIC CLR Q0
ADSC
ADSP DQ B,DQP B WRITE REGISTER DQ B,DQP B WRITE DRIVER MEMORY ARRAY BW A BWE GW CE1 CE2 CE3 OE ENABLE REGISTER DQ A, DQP A WRITE REGISTER DQ A, DQP A WRITE DRIVER SENSE AMPS
BW B
OUTPUT REGISTERS
OUTPUT BUFFERS
E
DQs DQP A DQP B
PIPELINED ENABLE
INPUT REGISTERS
ZZ
SLEEP CONTROL
Document #: 001-15143 Rev. *D
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Logic Block Diagram - CY7C1486BV25 (1M x 72)
A 0, A1,A
ADDRESS REGISTER
A[1:0]
MODE ADV CLK Q1 BINARY COUNTER CLR Q0
ADSC ADSP
BW H
DQ H, DQPH WRITE DRIVER DQ F, DQPF WRITE DRIVER DQ F, DQPF WRITE DRIVER DQ E, DQPE WRITE DRIVER DQ D, DQPD WRITE DRIVER
DQ H, DQPH WRITE DRIVER DQ G, DQPG WRITE DRIVER DQ F, DQPF WRITE DRIVER DQ E, DQPE BYTE "a" WRITE DRIVER DQ D, DQPD WRITE DRIVER DQ C, DQPC WRITE DRIVER
SENSE AMPS
BW G
BW F
BW E
MEMORY ARRAY
BW D
BW C
DQ C, DQPC WRITE DRIVER
OUTPUT REGISTERS
BW B
DQ B, DQPB WRITE DRIVER
DQ B, DQPB WRITE DRIVER DQ A , DQPA WRITE DRIVER
OUTPUT BUFFERS E
BW A BWE GW CE1 CE2 CE3 OE
DQ A , DQPA WRITE DRIVER
ENABLE REGISTER
PIPELINED ENABLE
INPUT REGISTERS
DQs DQP A DQP B DQP C DQP D DQP E DQP F DQP G DQP H
ZZ
SLEEP CONTROL
Document #: 001-15143 Rev. *D
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Pin Configurations
Figure 1. 100-Pin TQFP Pinout
A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQPC DQC DQc VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1480BV25 (2M x 36)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA
NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
CY7C1482BV25 (4M x 18)
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A A A A A1 A0 A A VSS VDD
MODE A A A A A1 A0 A A VSS VDD
A A A A A A A A A
Document #: 001-15143 Rev. *D
A A A A A A A A A
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Pin Configurations
(continued)
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout CY7C1480BV25 (2M x 36)
1 A B C D E F G H J K L M N P R
NC/288M NC/144M DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE
2
A A NC DQC DQC DQC DQC NC DQD DQD DQD DQD NC
A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE VSS VDD
9
ADV ADSP
10
A A NC/1G DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A
11
NC NC/576M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
A
A
A
CY7C1482BV25 (4M x 18)
1 A B C D E F G H J K L M N P R
NC/288M NC/144M NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE
2
A A NC DQB DQB DQB DQB NC NC NC NC NC NC
A
3
CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A
4
BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
5
NC BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI
TMS
6
CE3 CLK
7
BWE GW
8
ADSC OE
9
ADV ADSP
10
A A NC/1G NC NC NC NC NC DQA DQA DQA DQA NC A A
11
A NC/576M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A A1 A0
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK
VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS
A
VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A
A
A
A
A
Document #: 001-15143 Rev. *D
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Pin Configurations
(continued)
209-Ball FBGA (14 x 22 x 1.76 mm) Pinout CY7C1486BV25 (1M x 72)
1 A B C D E F G H J K L M N P R T U V W 2 3
A BWSC BWSH VSS VDDQ VSS VDDQ VSS VDDQ CLK VDDQ VSS VDDQ VSS
4
CE2
5
6
7
ADV A
8
CE3 BWSB
9
A BWSF BWSA VSS VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ VSS A A TCK
10
11
DQG DQG DQG DQG DQPG DQC DQC DQC DQC
NC
DQG DQG DQG DQG DQPC DQC DQC DQC DQC
NC
ADSP ADSC BWE
DQB DQB DQB DQB DQPF DQF DQF DQF DQF
NC
DQB DQB DQB DQB DQPB DQF DQF DQF DQF
NC
BWSG NC/288M
BWSD NC/144M CE1 NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDI NC/1G VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A OE VDD NC NC NC NC VSS NC NC NC ZZ VDD MODE A A1 A0
NC/576M BWSE GW VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD NC A A A NC VDDQ VSS VDDQ VSS VDDQ NC VDDQ VSS VDDQ VSS VDDQ NC A A TDO
DQH DQH DQH DQH DQPD DQD DQD DQD DQD
DQH DQH DQH DQH
DQA DQA DQA DQA DQPA DQE DQE DQE DQE
DQA DQA DQA DQA DQPE DQE DQE DQE DQE
DQPH VDDQ DQD DQD DQD DQD
VSS A A TMS
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Table 1. Pin Definitions Pin Name A0, A1, A IO InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous InputSynchronous InputSynchronous InputAsynchronous Description Address Inputs Used to Select One of the Address Locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled active. A1: A0 are fed to the two-bit counter. Byte Write Select Inputs, Active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. Global Write Enable Input, Active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Byte Write Enable Input, Active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Captures all synchronous inputs to the device. Also increments the burst counter when ADV is asserted LOW during a burst operation. Chip Enable 1 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. Chip Enable 2 Input, Active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when a new external address is loaded. Chip Enable 3 Input, Active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when a new external address is loaded. Output Enable, Asynchronous Input, Active LOW. Controls the direction of the IO pins. When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. Advance Input Signal, Sampled on the Rising Edge of CLK, Active LOW. When asserted, it automatically increments the address in a burst cycle. Address Strobe from Processor, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. Address Strobe from Controller, Sampled on the Rising Edge of CLK, Active LOW. When asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ZZ "Sleep" Input, Active HIGH. When asserted HIGH places the device in a non-time-critical "sleep" condition with data integrity preserved. For normal operation, this pin must be LOW or left floating. ZZ pin has an internal pull down. Bidirectional Data IO Lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state condition. Power Supply Inputs to the Core of the Device. Ground for the Core of the Device. Ground for the IO Circuitry.
BWA, BWB, BWC, BWD, BWE, BWF, BWG, BWH GW BWE CLK CE1
CE2
CE3
OE
ADV ADSP
InputSynchronous InputSynchronous
ADSC
InputSynchronous
ZZ
InputAsynchronous IOSynchronous
DQs, DQPs
VDD VSS VSSQ[2] VDDQ
Power Supply Ground IO Ground
IO Power Supply Power Supply for the IO Circuitry.
Note 2. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the IO circuitry.
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Table 1. Pin Definitions (continued) Pin Name MODE IO Input Static Description Selects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and must remain static during device operation. Mode pin has an internal pull up. Serial Data Out to the JTAG Circuit. Delivers data on the negative edge of TCK. If the JTAG feature is not used, this pin must be disconnected. This pin is not available on TQFP packages.
TDO
JTAG Serial Output Synchronous
TDI
JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG Serial Input Serial Data In to the JTAG Circuit. Sampled on the rising edge of TCK. If the JTAG feature Synchronous is not used, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG Clock Clock Input to the JTAG Circuitry. If the JTAG feature is not used, this pin must be connected to VSS. This pin is not available on TQFP packages. No Connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die. propagate through the output register and onto the data bus within 3.0 ns (250-MHz device) if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state; its outputs are always tri-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. After the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output tri-states immediately.
TMS
TCK NC
Functional Overview
All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (tCO) is 3.0 ns (250 MHz device). The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 supports secondary cache in systems using either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486TM processors. The linear burst sequence is suited for processors that use a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Three synchronous Chip Selects (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide easy bank selection and output tri-state control. ADSP is ignored if CE1 is HIGH.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1, CE2, CE3 are all asserted active. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP-triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH, then the BWE and BWX signals control the write operation. The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 provides Byte Write capability that is described in the "Truth Table for Read/Write" on page 11. Asserting the Byte Write Enable input (BWE) with the selected Byte Write (BWX) input, selectively writes to only the desired bytes. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism is provided to simplify the write operations. Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is a common IO device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so tri-states the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE.
Single Read Accesses
This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) CE1, CE2, CE3 are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs (A) is stored into the address advancement logic and the Address Register while being presented to the memory array. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to
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Single Write Accesses Initiated by ADSC
ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC-triggered write accesses need a single clock cycle to complete. The address presented to A is loaded into the address register and the address advancement logic while being delivered to the memory array. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQs is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 is a common IO device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQs inputs. Doing so tri-states the output drivers. As a safety precaution, DQs are automatically tri-stated whenever a write cycle is detected, regardless of the state of OE.
Sleep Mode
The ZZ input pin is asynchronous. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. Table 2. Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00
Burst Sequences
The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 provides a two-bit wraparound counter, fed by A1: A0, that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Asserting ADV LOW at clock rise automatically increments the burst counter to the next address in the burst sequence. Both read and write burst operations are supported.
Table 3. Linear Burst Address Table (MODE = GND) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10
ZZ Mode Electrical Characteristics
Parameter IDDZZ tZZS tZZREC tZZI tRZZI Description Sleep Mode Standby Current Device Operation to ZZ ZZ Recovery Time ZZ Active to Sleep Current ZZ Inactive to Exit Sleep Current Test Conditions ZZ > VDD - 0.2V ZZ > VDD - 0.2V ZZ < 0.2V This parameter is sampled This parameter is sampled 0 2tCYC 2tCYC Min Max 120 2tCYC Unit mA ns ns ns ns
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Table 4. Truth Table The truth table for CY7C1480BV25, CY7C1482BV25, and CY7C1486BV25 follows.[3, 4, 5, 6, 7] Operation Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Sleep Mode, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Add. Used None None None None None None External External External External External Next Next Next Next Next Next Current Current Current Current Current Current CE1 H L L L L X L L L L L X X H H X H X X H H X H CE2 X L X L X X H H H H H X X X X X X X X X X X X CE3 X X H X H X L L L L L X X X X X X X X X X X X ZZ L L L L L H L L L L L L L L L L L L L L L L L ADSP X L L H H X L L H H H H H X X H X H H X X H X ADSC L X X L L X X X L L L H H H H H H H H H H H H ADV X X X X X X X X X X X L L L L L L H H H H H H WRITE X X X X X X X X L H H H H H H L L H H H H L L OE CLK X X X X X X L H X L H L H L H X X L H L H X X L-H L-H L-H L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ Tri-State Tri-State Tri-State Tri-State Tri-State Tri-State Q Tri-State D Q Tri-State Q Tri-State Q Tri-State D D Q Tri-State Q Tri-State D D
Notes 3. X = Do Not Care, H = Logic HIGH, L = Logic LOW. 4. WRITE = L when any one or more Byte Write Enable signals and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals, BWE, GW = H. 5. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock. 6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to enable the outputs to tri-state. OE is a do not care for the remainder of the write cycle 7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Table 5. Truth Table for Read/Write The read-write truth table for the CY7C1480BV25 follows.[5] Function (CY7C1480BV25) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Bytes B, A Write Byte C - (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D - (DQD and DQPD) Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X BWD X H H H H H H H H L L L L L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X
Table 6. Truth Table for Read/Write The read-write truth table for the CY7C1482BV25 follows.[5] Function (CY7C1482BV25) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Bytes B, A Write All Bytes Write All Bytes Table 7. Truth Table for Read/Write The read-write truth table for the CY7C1486BV25 follows.[8] Function (CY7C1486BV25) Read Read Write Byte x - (DQx and DQPx) Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BWX X All BW = H L All BW = L X GW H H H H H H L BWE H L L L L L X BWB X H H L L L X BWA X H L H L L X
Note 8. BWx represents any byte write signal BW[0..7]. To enable any byte write BWx, a Logic LOW signal must be applied at clock rise. Any number of byte writes can be enabled at the same time for a supplied write.
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IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 2.5V IO logic levels. The CY7C1480BV25/CY7C1482BV25/CY7C1486BV25 contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Test Mode Select (TMS) The TMS input gives commands to the TAP controller and is sampled on the rising edge of TCK. You can leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball serially inputs information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information about loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See TAP Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. Whether the output is active depends on the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See TAP Controller State Diagram.) Figure 3. TAP Controller Block Diagram
0
1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCA N 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 1 0 1
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, tie TCK LOW (VSS) to prevent device clocking. TDI and TMS are internally pulled up and may be unconnected. They may alternatively be connected to VDD through a pull up resistor. TDO must be left unconnected. At power up, the device comes up in a reset state, which does not interfere with the operation of the device. Figure 2. TAP Controller State Diagram
Bypass Register
210
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
TCK
PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0
TM S
TAP CONTROLLER
Performing a TAP Reset
Perform a RESET by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
TAP Registers
Registers are connected between the TDI and TDO balls to scan the data in and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
Test Access Port (TAP)
Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
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Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the "TAP Controller Block Diagram" on page 12. At power up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to enable fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This shifts data through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The x36 configuration has a 73-bit-long register, and the x18 configuration has a 54-bit-long register. The boundary scan register is loaded with the contents of the RAM IO ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller moves to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the IO ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in "Identification Register Definitions" on page 15. rather, it performs a capture of the IO ring when these instructions are executed. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction after it is shifted in, the TAP controller must be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction that is executed whenever the instruction register is loaded with all zeros. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-zero instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO balls and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is in a test logic reset state. SAMPLE Z The SAMPLE Z instruction connects the boundary scan register between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1 compliant. When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. Be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output may undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This does not harm the device, but there is no guarantee as to the value that may be captured. Repeatable results may not be possible. To guarantee that the boundary scan register captures the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a
TAP Instruction Set
Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in "Identification Codes" on page 16. Three of these instructions are listed as RESERVED and must not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the IO buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; Document #: 001-15143 Rev. *D
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SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CLK captured in the boundary scan register. After the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls. Note that because the PRELOAD part of the command is not implemented, putting the TAP to the Update-DR state while performing a SAMPLE/PRELOAD instruction has the same effect as the Pause-DR command. Figure 4. TAP Timing
1 Test Clock (TCK)
t TMSS t TH t TMSH t TL t CYC
BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions.
2
3
4
5
6
Test Mode Select (TMS)
t TDIS t TDIH
Test Data-In (TDI)
t TDOV t TDOX
Test Data-Out (TDO) DON'T CARE UNDEFINED
TAP AC Switching Characteristics
Over the Operating Range[9, 10] Parameter Clock tTCYC tTF tTH tTL tTDOV tTDOX Setup Times tTMSS tTDIS tCS Hold Times tTMSH tTDIH tCH TMS Hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise 5 5 5 ns ns ns TMS Setup to TCK Clock Rise TDI Setup to TCK Clock Rise Capture Setup to TCK Rise 5 5 5 ns ns ns TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH Time TCK Clock LOW Time TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid 0 20 20 10 50 20 ns MHz ns ns ns ns Description Min Max Unit
Output Times
Notes 9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
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2.5V TAP AC Test Conditions
Input pulse levels................................................. VSS to 2.5V Input rise and fall time .....................................................1 ns Input timing reference levels......................................... 1.25V Output reference levels ................................................ 1.25V Test load termination supply voltage ............................ 1.25V Figure 5. 2.5V TAP AC Output Load Equivalent
1.25V 50 TDO Z O= 50 20pF
TAP DC Electrical Characteristics And Operating Conditions
(0C < TA < +70C; VDD = 2.5V 0.125V unless otherwise noted)[11] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current Test Conditions IOH = -1.0 mA, VDDQ = 2.5V IOH = -100 A, VDDQ = 2.5V IOL = 1.0 mA, VDDQ = 2.5V IOL = 100 A, VDDQ = 2.5V VDDQ = 2.5V VDDQ = 2.5V GND VI VDDQ 1.7 -0.3 -5 Min 1.7 2.1 0.4 0.2 VDD + 0.3 0.7 5 Max Unit V V V V V V A
Table 8. Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24) Architecture/Memory Type(23:18) Bus Width/Density(17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) Table 9. Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Order - 165FBGA Boundary Scan Order - 209BGA
Note 11. All voltages refer to VSS (GND).
CY7C1480BV25 (2M x36) 000 01011 000000 100100 00000110100 1
CY7C1482BV25 (4M x 18) 000 01011 000000 010100 00000110100 1
CY7C1486BV25 (1M x72) 000 01011 000000 110100 00000110100 1
Description Describes the version number Reserved for internal use Defines memory type and architecture Defines width and density Enables unique identification of SRAM vendor Indicates the presence of an ID register
Bit Size (x36) 3 1 32 73 -
Bit Size (x18) 3 1 32 54 -
Bit Size (x72) 3 1 32 112
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Table 10. Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Captures the IO ring contents. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures the IO ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures the IO ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. Description
Table 11. Boundary Scan Exit Order (2M x 36) Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 165-Ball ID C1 D1 E1 D2 E2 F1 G1 F2 G2 J1 K1 L1 J2 M1 N1 K2 L2 M2 R1 R2 Bit # 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 165-Ball ID R3 P2 R4 P6 R6 N6 P11 R8 P3 P4 P8 P9 P10 R9 R10 R11 N11 M11 L11 M10 Bit # 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 165-Ball ID L10 K11 J11 K10 J10 H11 G11 F11 E11 D10 D11 C11 G10 F10 E10 A10 B10 A9 B9 A8 Bit # 61 62 63 64 65 66 67 68 69 70 71 72 73 165-Ball ID B8 A7 B7 B6 A6 B5 A5 A4 B4 B3 A3 A2 B2
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Boundary Scan Exit Order (4M x 18)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 165-Ball ID D2 E2 F2 G2 J1 K1 L1 M1 N1 R1 R2 R3 P2 R4 P6 R6 N6 P11 Bit # 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 165-Ball ID R8 P3 P4 P8 P9 P10 R9 R10 R11 M10 L10 K10 J10 H11 G11 F11 E11 D11 Bit # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 165-Ball ID C11 A11 A10 B10 A9 B9 A8 B8 A7 B7 B6 A6 B5 A4 B3 A3 A2 B2
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Boundary Scan Exit Order (1M x 72)
Bit # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 209-Ball ID A1 A2 B1 B2 C1 C2 D1 D2 E1 E2 F1 F2 G1 G2 H1 H2 J1 J2 L1 L2 M1 M2 N1 N2 P1 P2 R2 R1 Bit # 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 209-Ball ID T1 T2 U1 U2 V1 V2 W1 W2 T6 V3 V4 U4 W5 V6 W6 U3 U9 V5 U5 U6 W7 V7 U7 V8 V9 W11 W10 V11 Bit # 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 209-Ball ID V10 U11 U10 T11 T10 R11 R10 P11 P10 N11 N10 M11 M10 L11 L10 P6 J11 J10 H11 H10 G11 G10 F11 F10 E10 E11 D11 D10 Bit # 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 209-Ball ID C11 C10 B11 B10 A11 A10 A9 U8 A7 A5 A6 D6 B6 D7 K3 A8 B4 B3 C3 C4 C8 C9 B9 B8 A4 C6 B7 A3
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Maximum Ratings
Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................ -55C to +125C Supply Voltage on VDD Relative to GND ........-0.3V to +3.6V Supply Voltage on VDDQ Relative to GND.......-0.3V to +VDD DC Voltage Applied to Outputs in Tri-State ........................................... -0.5V to VDDQ + 0.5V DC Input Voltage ................................... -0.5V to VDD + 0.5V Current into Outputs (LOW) ........................................ 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch Up Current .................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VDD VDDQ
2.5V -5%/+5% 2.5V-5% to VDD
Electrical Characteristics
Over the Operating Range[12, 13] Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage IO Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[12] Input LOW Voltage[12] Input Leakage Current except ZZ and MODE Input Current of MODE Input Current of ZZ IOZ IDD
[14]
Test Conditions For 2.5V IO For 2.5V IO, IOH = -1.0 mA For 2.5V IO, IOL = 1.0 mA For 2.5V IO For 2.5V IO GND VI VDDQ Input = VSS Input = VDD Input = VSS Input = VDD
Min 2.375 2.375 2.0
Max 2.625 VDD 0.4
Unit V V V V V V A A
1.7 -0.3 -5 -30
VDD + 0.3V 0.7 5
5 -5 30 -5 4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz 4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz All speeds 5 450 450 400 200 200 200 120
A A A A mA mA mA mA mA mA mA
Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current VDD = Max, IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN 0.3V or VIN > VDDQ - 0.3V, f=0 VDD = Max, Device Deselected, or VIN 0.3V or VIN > VDDQ - 0.3V f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN VIH or VIN VIL, f = 0
ISB1
Automatic CE Power Down Current--TTL Inputs Automatic CE Power Down Current--CMOS Inputs Automatic CE Power Down Current--CMOS Inputs Automatic CE Power Down Current--TTL Inputs
ISB2
ISB3
4.0-ns cycle, 250 MHz 5.0-ns cycle, 200 MHz 6.0-ns cycle, 167 MHz All speeds
200 200 200 135
mA mA mA mA
ISB4
Notes 12. Overshoot: VIH(AC) < VDD +1.5V (pulse width less than tCYC/2).Undershoot: VIL(AC) > -2V (pulse width less than tCYC/2). 13. Power up: assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD. 14. The operation current is calculated with 50% read cycle and 50% write cycle.
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Capacitance
Tested initially and after any design or process change that may affect these parameters. Parameter CADDRESS CDATA CCTRL CCLK CIO Description Address Input Capacitance Data Input Capacitance Control Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 2.5V VDDQ = 2.5V 100 TQFP Package 6 5 8 6 5 165 FBGA Package 6 5 8 6 5 209 FBGA Package 6 5 8 6 5 Unit pF pF pF pF pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters. Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 100 TQFP Max 24.63 2.28 165 FBGA Max 16.3 2.1 209 FBGA Max 15.2 1.7 Unit C/W C/W
AC Test Loads and Waveforms
2.5V IO Test Load
R = 1667 ALL INPUT PULSES VDDQ 10% 5 pF R = 1583 GND 1 ns 90% 90% 10% 1 ns
OUTPUT Z0 = 50
2.5V OUTPUT RL = 50
VL = 1.25V
(a)
INCLUDING JIG AND SCOPE
(b)
(c)
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Switching Characteristics
Over the Operating Range. Timing reference level is 1.25V when VDDQ = 2.5V. Test conditions shown in (a) of "AC Test Loads and Waveforms" on page 20 unless otherwise noted. Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Setup Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold After CLK Rise ADSP, ADSC Hold After CLK Rise ADV Hold After CLK Rise GW, BWE, BWX Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns ns Address Setup Before CLK Rise ADSC, ADSP Setup Before CLK Rise ADV Setup Before CLK Rise GW, BWE, BWX Setup Before CLK Rise Data Input Setup Before CLK Rise Chip Enable Setup Before CLK Rise 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.5 1.5 1.5 1.5 ns ns ns ns ns ns Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Clock to Low-Z[16, 17, 18] High-Z[16, 17, 18] Low-Z[16, 17, 18] High-Z[16, 17, 18] 0 3.0 1.3 1.3 3.0 3.0 0 3.0 3.0 1.3 1.3 3.0 3.0 0 3.4 3.0 1.5 1.5 3.4 3.4 3.4 ns ns ns ns ns ns ns Clock Cycle Time Clock HIGH Clock LOW 4.0 2.0 2.0 5.0 2.0 2.0 6.0 2.4 2.4 ns ns ns Description VDD(Typical) to the first access[15] 250 MHz Min 1 Max 200 MHz Min 1 Max 167 MHz Min 1 Max Unit ms
OE LOW to Output Valid OE LOW to Output OE HIGH to Output
Notes 15. This part has an internal voltage regulator; tPOWER is the time that the power is supplied above VDD(minimum) initially before a read or write operation can be initiated. 16. tCHZ, tCLZ, tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of "AC Test Loads and Waveforms" on page 20. Transition is measured 200 mV from steady-state voltage. 17. At any possible voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z before Low-Z under the same system conditions. 18. This parameter is sampled and not 100% tested.
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Switching Waveforms
Timing for the read cycle is shown in Figure 6.[19] Figure 6. Read Cycle Timing
t CYC
CLK t CH t CL
t
ADS
t ADH
ADSP t ADS ADSC t AS A1 t WES GW, BWE, BWx t CES CE t ADVS ADV ADV suspends burst. OE t OEV t OEHZ t CLZ Data Out (Q) High-Z Q(A1) t CO Burst wraps around to its initial state Single READ BURST READ t OELZ Q(A2) t CO t DOH Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) t CHZ Q(A2 + 1) tADVH tCEH Deselect cycle tWEH tAH tADH
ADDRESS
A2
A3 Burst continued with new base address
DON'T CARE
UNDEFINED
Note 19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
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Switching Waveforms (continued)
Timing for the write cycle is shown in Figure 7.[19, 20] Figure 7. Write Cycle Timing
t CYC
CLK tCH t ADS ADSP ADSC extends burst t ADS tADH tADH tCL
t ADS ADSC t AS A1 tAH
tADH
ADDRESS
A2 Byte write signals are ignored for first cycle when ADSP initiates burst
A3
t WES tWEH
BWE, BW X t WES tWEH GW t CES CE t t ADVS ADVH ADV ADV suspends burst tCEH
OE t DS tDH
Data In (D)
High-Z
t OEHZ
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q) BURST READ Single WRITE BURST WRITE Extended BURST WRITE
DON'T CARE
UNDEFINED
Note 20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.
Document #: 001-15143 Rev. *D
Page 23 of 31
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Switching Waveforms (continued)
Timing for the read-write cycle is shown in Figure 8.[19, 21, 22] Figure 8. Read/Write Cycle Timing
tCYC
CLK tCH t ADS ADSP tADH tCL
ADSC t AS tAH
ADDRESS
A1
A2
A3 t WES tWEH
A4
A5
A6
BWE, BWX
t CES CE
tCEH
ADV
OE tCO t DS tDH t OELZ Data In (D) High-Z tCLZ Data Out (Q) High-Z Q(A1) Back-to-Back READs tOEHZ Q(A2) Single WRITE D(A3) D(A5) D(A6)
Q(A4)
Q(A4+1) BURST READ
Q(A4+2)
Q(A4+3) Back-to-Back WRITEs
DON'T CARE
UNDEFINED
Notes 21. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC. 22. GW is HIGH.
Document #: 001-15143 Rev. *D
Page 24 of 31
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Switching Waveforms (continued)
Timing for ZZ mode is shown in Figure 9.[23, 24] Figure 9. ZZ Mode Timing
CLK
t ZZ t ZZREC
ZZ
t ZZI
I
SUPPLY I DDZZ t RZZI DESELECT or READ Only
ALL INPUTS (except ZZ)
Outputs (Q)
High-Z
DON'T CARE
Notes 23. Device must be deselected when entering ZZ mode. See "Truth Table" on page 10 for all possible signal conditions to deselect the device. 24. DQs are in high-Z when exiting ZZ sleep mode.
Document #: 001-15143 Rev. *D
Page 25 of 31
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Ordering Information
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 167 Ordering Code CY7C1480BV25-167AXC CY7C1482BV25-167AXC CY7C1480BV25-167BZC CY7C1482BV25-167BZC CY7C1480BV25-167BZXC CY7C1482BV25-167BZXC CY7C1486BV25-167BGC CY7C1486BV25-167BGXC CY7C1480BV25-167AXI CY7C1482BV25-167AXI CY7C1480BV25-167BZI CY7C1482BV25-167BZI CY7C1480BV25-167BZXI CY7C1482BV25-167BZXI CY7C1486BV25-167BGI CY7C1486BV25-167BGXI 200 CY7C1480BV25-200AXC CY7C1482BV25-200AXC CY7C1480BV25-200BZC CY7C1482BV25-200BZC CY7C1480BV25-200BZXC CY7C1482BV25-200BZXC CY7C1486BV25-200BGC CY7C1486BV25-200BGXC CY7C1480BV25-200AXI CY7C1482BV25-200AXI CY7C1480BV25-200BZI CY7C1482BV25-200BZI CY7C1480BV25-200BZXI CY7C1482BV25-200BZXI CY7C1486BV25-200BGI CY7C1486BV25-200BGXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free Commercial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Pb-Free 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free lndustrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Pb-Free
Document #: 001-15143 Rev. *D
Page 26 of 31
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Ordering Information
(continued)
Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com for actual products offered. Speed (MHz) 250 Ordering Code CY7C1480BV25-250AXC CY7C1482BV25-250AXC CY7C1480BV25-250BZC CY7C1482BV25-250BZC CY7C1480BV25-250BZXC CY7C1482BV25-250BZXC CY7C1486BV25-250BGC CY7C1486BV25-250BGXC CY7C1480BV25-250AXI CY7C1482BV25-250AXI CY7C1480BV25-250BZI CY7C1482BV25-250BZI CY7C1480BV25-250BZXI CY7C1482BV25-250BZXI CY7C1486BV25-250BGI CY7C1486BV25-250BGXI 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) 51-85167 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) 209-ball Fine-Pitch Ball Grid Array (14 x 22 x 1.76 mm) Lead-Free 51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free Industrial 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Lead-Free 51-85165 165-ball Fine-Pitch Ball Grid Array (15 x 17 x 1.4 mm) Package Diagram Part and Package Type Operating Range Commercial
51-85050 100-Pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free
Document #: 001-15143 Rev. *D
Page 27 of 31
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Package Diagrams
Figure 10. 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm), 51-85050
16.000.20 14.000.10
100 1 81 80
1.400.05
0.300.08
22.000.20
20.000.10
0.65 TYP.
30 31 50 51
121 (8X)
SEE DETAIL
A
0.20 MAX. 1.60 MAX. 0 MIN. SEATING PLANE 0.25 GAUGE PLANE STAND-OFF 0.05 MIN. 0.15 MAX.
NOTE: 1. JEDEC STD REF MS-026 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH 3. DIMENSIONS IN MILLIMETERS
0-7
R 0.08 MIN. 0.20 MAX.
0.600.15 0.20 MIN. 1.00 REF.
DETAIL
51-85050-*B
A
Document #: 001-15143 Rev. *D
0.10
R 0.08 MIN. 0.20 MAX.
Page 28 of 31
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Package Diagrams
(continued) Figure 11. 165-Ball FBGA (15 x 17 x 1.4 mm), 51-85165
BOTTOM VIEW TOP VIEW O0.05 M C PIN 1 CORNER O0.25 M C A B
PIN 1 CORNER
O0.450.05(165X)
1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1
A B
A B
D E F G
1.00
C
C D E F G
17.000.10
H J K
14.00
H J K
M N P R
7.00
L
L M N P R
A 5.00 10.00 0.530.05 0.25 C
+0.05 -0.10
1.00
0.35
0.15 C
B 0.15(4X)
15.000.10
SEATING PLANE C 0.36 1.40 MAX.
51-85165-*A
Document #: 001-15143 Rev. *D
Page 29 of 31
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Package Diagrams
(continued) Figure 12. 209-Ball FBGA (14 x 22 x 1.76 mm), 51-85167
51-85167-**
Document #: 001-15143 Rev. *D
Page 30 of 31
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CY7C1480BV25 CY7C1482BV25, CY7C1486BV25
Document History Page
Document Title: CY7C1480BV25/CY7C1482BV25/CY7C1486BV25, 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM Document Number: 001-15143 REV. ** *A *B *C *D ECN NO. Issue Date 1024385 1562944 1897447 2082487 2159486 See ECN See ECN See ECN See ECN See ECN Orig. of Change VKN/KKVTMP New Data Sheet VKN/AESA VKN/AESA VKN VKN/PYRS Removed 1.8V IO offering from the data sheet Added footnote 14 related to IDD Converted from preliminary to final Minor Change-Moved to the external web Description of Change
(c) Cypress Semiconductor Corporation, 2007-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-15143 Rev. *D
Revised February 29, 2008
Page 31 of 31
NoBL and No Bus Latency are trademarks of Cypress Semiconductor Corporation. ZBT is a trademark of Integrated Device Technology, Inc. All products and company names mentioned in this document may be the trademarks of their respective holders.
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